RISC-V Day Tokyo 2026 Autumn — AI時代のオープンアーキテクチャ最前線

For English Please Scroll Down イベント詳細 名称:RISC-V Day Tokyo 2026 Autumn 日時:2026年11月11日(水) 会場:東京大学 本郷キャンパス 主催:一般社団法人 RISC-V協会 運営:SHコンサルティング株式会社 参加形態:事前登録制(参加登録は近日開始予定) 参加定員:約400名 プログラム:https://riscv.or.jp/risc-v-day-tokyo-2026-autumn/ 内容・見どころ 今回のRISC-V Dayは、RISC-Vの実装技術、半導体チップ試作、組込みシステム、AI、オープンソース・ハードウェアを中心とする技術特化型イベントです。午前はチップを設計する。午後は実物のチップを見る。という一日構成が特徴です。 午前:半導体チップ試作チュートリアル デジタル論理設計・チップ試作、アナログ回路設計・チップ試作の2トラックを並行開催。回路設計から検証、レイアウト、GDS作成、チップ試作までの流れを学べます。 午後:技術講演・特別展示 Google TPU v3の実機、Apple創立50周年記念のApple-1復刻機・iMac G3など、パーソナルコンピュータの原点から現代の大規模AIコンピューティングまでを実物で辿れます。Keynote、Main Forum、Technical Trackに加え、RISC-V関連企業・団体による技術展示、書籍展示・販売も予定。 来場者特典(新刊予告) 好評をいただいた『日本の半導体戦略 2024+1/2』の最新版として、『日本の半導体戦略 2026+1/2 NVIDIAと挑むAIチップ企業群』(ソハコ出版局刊)を刊行予定。来場者の皆様には本書を進呈いたします。当日の刊行が間に合わない場合は、後日郵送にてお届けいたします。 チケット2(日本語)：　インバータ回路設計・チップ試作基礎コース　(Inverter Circuit Design Tutorial with Chip Fabrication) 価格:¥3,000 定員:60名 説明文 半導体回路設計の入門として、インバータ回路の設計を題材にしたチュートリアルです。回路設計からSPICEシミュレーション、レイアウト、DRC/LVS検証、そしてテープアウトまでの流れを、実際に手を動かしながら学びます。 設計いただいたインバータは、既成のインバータと組み合わせてリング発振回路を構成し、発振性能を測定することでご自身の設計特性を評価いただきます。 設計いただいた回路は、GlobalFoundries 180nmプロセスのシャトルサービスで実際にチップ試作します。試作チップには、Tensor Toyメンバー3名の拠出により実現したRISC-V CPUとAI SRAM(決定論的なAI処理のため、アクセスタイムでなくサイクルタイムを最適化)が既に搭載されており、そのダイの余剰スペースに、本チュートリアル参加者60名分のインバータ回路を相乗りで試作します。 試作チップは1人あたり4個をお渡しする予定です。ただし製造プロセスの特性上、不良品が含まれる場合があります。評価・動作確認は、次回RISC-V Day(2027年5月19日開催予定)で行います。 ※本チケットには試作費用が含まれます。定員に達し次第、受付を終了いたします。 タイムテーブル(予定) ※講演者・詳細プログラムは順次発表。以下は暫定フォーマットイメージです。 主催・運営者情報 主催者:RISC-V協会(一般社団法人) 代表理事:河崎俊平 所在地:東京都中央区銀座7-18-13-502(協会事務局) 過去の活動:RISC-V Day Tokyoは2017年から毎年開催されており、国内最大級のRISC-V技術カンファレンスとして定着しています。 キャンセルポリシー・参加登録 参加登録は近日開始予定です。詳細が決まり次第、本ページにてご案内いたします。 Event Details Event Name: RISC-V Day Tokyo 2026 Autumn Date: Wednesday, November 11, 2026 Venue: The University of Tokyo, Hongo Campus Organizer: RISC-V Alliance Japan (General Incorporated Association) Event Management: SH Consulting K.K. Participation: Advance registration required (registration to open soon) Program Information: https://riscv.or.jp/en/risc-v-day-tokyo-2026-autumn-2/ Ticket 2 (English)　Inverter Circuit Design Tutorial with Chip Fabrication Price: ¥3,000 Capacity: 60 attendees Description An introductory course in semiconductor circuit design, centered on designing an inverter circuit. Participants learn the full flow — circuit design, SPICE simulation, layout, DRC/LVS verification, and tapeout — through hands-on work. Your designed inverter will be combined with pre-existing inverters to form a ring oscillator, allowing you to evaluate your design's characteristics by measuring its oscillation performance. The circuit will be fabricated via a GlobalFoundries 180nm process shuttle run. The shuttle die already includes a RISC-V CPU and an AI SRAM — optimized for cycle time rather than access time, enabling deterministic AI processing — funded by three members of Tensor Toy. The remaining die area will be shared among up to 60 tutorial participants for their own inverter designs. Each participant will receive 4 fabricated chips. Please note that, due to the nature of the fabrication process, some chips may not pass functional testing. Evaluation and testing will take place at the next RISC-V Day, scheduled for May 19, 2027. This ticket price covers fabrication costs. Registration will close once capacity is reached. Content & Highlights This RISC-V Day is a technology-focused event centered on RISC-V implementation, semiconductor chip prototyping, embedded systems, AI, and open-source hardware. The day is structured around a simple concept: in the morning, you design a chip. In the afternoon, you see the real thing. Morning: Semiconductor Chip Prototyping Tutorials Two parallel tracks — Digital Logic Design and Analog Circuit Design — covering the full flow from circuit design and verification to layout, GDS generation, and chip prototyping. Afternoon: Technical Sessions & Special Exhibits A real Google TPU v3 unit will be on display, alongside a replica Apple-1 and an Apple iMac G3 in celebration of Apple's 50th anniversary — tracing the path from the origins of personal computing to today's large-scale AI computing. The afternoon also includes Keynote, Main Forum, and Technical Track sessions, exhibits from RISC-V–related companies and organizations, and a book fair. Attendee Gift (Upcoming Publication) As a sequel to the well-received Japan's Semiconductor Strategy 2024+1/2, a new edition — Japan's Semiconductor Strategy 2026+1/2: AI Chip Companies Challenging NVIDIA (published by Sohaco Press) — is planned for release. Attendees will receive a copy on-site. If publication is not ready in time for the event, copies will be mailed afterward. Tentative Schedule Detailed speakers and session topics have not yet been announced. The following represents the preliminary format; the official version will be published soon. Organizer & Management Information Organizer: RISC-V Alliance Japan (General Incorporated Association) Representative Director: Shumpei Kawasaki Office Location: 7-18-13-502 Ginza, Chuo-ku, Tokyo (Association Secretariat) Past Activities: RISC-V Day Tokyo has been held annually since 2017 and has become one of the largest and most established RISC-V technical conferences in Japan. Cancellation Policy & Registration Registration will open soon. Details will be announced on this page once finalized. Content & Highlights This RISC-V Day is a technology-focused event centered on RISC-V implementation, semiconductor chip prototyping, embedded systems, AI, and open-source hardware. The day is structured around a simple concept: in the morning, you design a chip. In the afternoon, you see the real thing. Morning: Semiconductor Chip Prototyping Tutorials Two parallel tracks — Digital Logic Design and Analog Circuit Design — covering the full flow from circuit design and verification to layout, GDS generation, and chip prototyping. Afternoon: Technical Sessions & Special Exhibits A real Google TPU v3 unit will be on display, alongside a replica Apple-1 and an Apple iMac G3 in celebration of Apple's 50th anniversary — tracing the path from the origins of personal computing to today's large-scale AI computing. The afternoon also includes Keynote, Main Forum, and Technical Track sessions, exhibits from RISC-V–related companies and organizations, and a book fair. Attendee Gift (Upcoming Publication) As a sequel to the well-received Japan's Semiconductor Strategy 2024+1/2, a new edition — Japan's Semiconductor Strategy 2026+1/2: AI Chip Companies Challenging NVIDIA (published by Sohaco Press) — is planned for release. Attendees will receive a copy on-site. If publication is not ready in time for the event, copies will be mailed afterward. Tentative Schedule Detailed speakers and session topics have not yet been announced. The following represents the preliminary format; the official version will be published soon. Time Session Morning (from ~9:00) Registration; Semiconductor Chip Prototyping Tutorials (Digital Logic Design / Analog Circuit Design, two parallel tracks) Midday Lunch & Technical Networking Afternoon Keynote / Main Forum / Technical Track; Google TPU v3 & Chip Museum Special Exhibits; Corporate Technical Exhibits Evening Closing Remarks Organizer & Management Information Organizer: RISC-V Alliance Japan (General Incorporated Association) Representative Director: Shumpei Kawasaki Office Location: 7-18-13-502 Ginza, Chuo-ku, Tokyo (Association Secretariat) Past Activities: RISC-V Day Tokyo has been held annually since 2017 and has become one of the largest and most established RISC-V technical conferences in Japan. Cancellation Policy & Registration Registration will open soon. Details will be announced on this page once finalized.